Εκπαίδευση - Σπουδές

ΕΛΛΗΝΙΚΟ ΑΝΟΙΚΤΟ ΠΑΝΕΠΙΣΤΉΜΙΟ ΣΧΟΛΗ ΘΕΤΙΚΩΝ ΕΠΙΣΤΗΜΩΝ ΚΑΙ ΤΕΧΝΟΛΟΓΙΑΣ Πτυχίο Πληροφορικής

ΠΑΝΕΠΙΣΤΉΜΙΟ ΑΙΓΑΙΟΥ Τμήμα Μηχανικών Πληροφοριακών & Επικοινωνιακών Συστημάτων Πρόγραμμα Μεταπτυχιακών Σπουδών: Τεχνολογίες και Διοίκηση Πληροφοριακών και Επικοινωνιακών Συστημάτων Κατεύθυνση 4 - Τεχνολογίες Δικτύων Επικοινωνιών και Υπολογιστών

Ερευνητικά Ενδιαφέροντα

Hardware Security

Διδασκαλία

Δημοσιεύσεις σε Διεθνή Περιοδικά (Journals)


Copyright Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted or mass reproduced without the explicit permission of the copyright holder.


Επιστημονικά Συνέδρια (Conferences)


Copyright Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted or mass reproduced without the explicit permission of the copyright holder.


E. Kalligeros, N. Karousos, I. G. Karybali, "Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist", Design Automation and Test in Europe (DATE) Conference, (to_appear), Mar, 2020,
 

Abstract
Logic locking has received a lot of attention in the literature due to its very attractive hardware-security characteristics: it can protect against IP piracy and overproduction throughout the whole IC supply chain. However, a large class of logic-locking attacks, the oracle-based ones, take advantage of a functional copy of the chip, the oracle, to extract the key that protects the chip. So far, the techniques dealing with oracle-based attacks focus on the netlist that the attacker possesses, assuming that the oracle is always available. For this reason, they are usually overcome by new attacks. In this paper, we propose a hardware security scheme that targets the protection of the oracle circuit, by locking the circuit when the, necessary for setting the inputs and observing the outputs, scan in/out process begins. Hence, no correct input/output pairs can be acquired to perform the attacks. The proposed scheme is not based on controlling global signals like test_enable or scan_enable, whose values can be easily suppressed by the attacker. Security threats are identified, discussed and addressed. The developed scheme is combined with a traditional logic locking technique with high output corruptibility, to achieve increased levels of protection.

N. Karousos, K. Pexaras, I. G. Karybali, E. Kalligeros, "Weighted Logic Locking: A New Approach for IC Piracy Protection", IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 221-226, Jul, 2017, http://ieeexplore.ieee.org/stamp/st...
 

Abstract
Logic locking has been successfully used for protecting digital circuits against IC piracy. Modern logic locking techniques offer significant security advantages, like high corruptibility of the locked circuit's outputs when applying random keys (= 50% Hamming Distance -HD- compared to the correct outputs), or resilience to the key-sensitization attack. However, there are no techniques to combine both advantages. To solve this problem, weighted logic locking is proposed in this paper. Instead of the conventional single key-input control, the proposed technique uses multiple key-inputs to control every key-gate. This new, weighted key-gate control is by construction immune to the key-sensitization attack, while by employing a new key-gate insertion metric, 50% HD is obtained even for circuits with many outputs. Additionally, weighted key-gate control increases dramatically the probability of any key-gate to corrupt the circuit’s values, which means that fewer key-gates are needed to achieve 50% HD. This way, execution time for locking the circuits is drastically reduced. Apart from these advantages, weighted logic locking is fairly "generic" and can be combined with other techniques to improve security (e.g., to thwart the SAT attack).

Βιβλία


Copyright Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted or mass reproduced without the explicit permission of the copyright holder.


Κεφάλαια σε Βιβλία


Copyright Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted or mass reproduced without the explicit permission of the copyright holder.


Επιμέλεια Πρακτικών Διεθνών Συνεδρίων


Copyright Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted or mass reproduced without the explicit permission of the copyright holder.