|Σχεδίαση Ψηφιακών Συστημάτων|
|Title: ||Σχεδίαση Ψηφιακών Συστημάτων|
|Lesson Code: ||321-7051|
|Theory Hours: ||3|
|Lab Hours: ||2|
|Faculty: ||Kalligeros Emmanouil|
Application Specific Integrated Circuits (ASICs) and programmable devices (PLAs, PLDs, FPGAs), Hardware Description Languages (HDLs): Verilog and VHDL. Introduction to Verilog HDL, designing digital circuits with Verilog, Verilog syntax, modules and ports, structural modeling, behavioral modeling, dataflow modeling, tasks and functions. Finite State Machines (Mealy and Moore), Verilog for synthesis, design of sequential modules. Timing and delays in Verilog, Computer Aided Design (CAD) tools, logical simulation and timing verification. Random Access Memories (RAMs) and memory interfaces. Design prototyping.
Students who successfully fulfill the course requirements will know: the differences between programmable devices and ASICs, the main features of FPGAs structure, how to use Verilog HDL for designing combinational and sequential digital circuits, how to write testbenches in Verilog, how to write Verilog for synthesis, how to simulate their designs, the structure of RAMs and how to use them in digital systems, how to use prototyping boards for transferring their designs in hardware.
Logic Design (321-2003), Circuit Theory (321-2551), Computer Architecture (321-3354)
- Digital Design, A Systems Approach, W. J. Dally, R. C. Harting
- FPGA-Based System Design, Wayne Wolf
- Verilog HDL: A Guide to Digital Design and Synthesis, Samir Palnitkar, 2nd Ed.
- IEEE Transactions on VLSI Systems
- IEEE Transactions on Computers
|Learning Activities and Teaching Methods |
Lab exercises (20%), Project (40%), Written examination (40%)
|Assessment/Grading Methods |
Lectures, Lab exercises, Project
|Language of Instruction|
|Greek, English (for Erasmus students)|
|Μode of delivery |