Department of Information & Communication Systems Engineering
University of the Aegean

Department of Information
& Communication Systems Engineering

Information & Communication Systems Security
Information Systems
Artificial Intelligence
Computer & Communication Systems
Geometry, Dynamical Systems & Cosmology
Digital Systems Design

Title: Digital Systems Design
Lesson Code: 321-7051
Semester: 7
Theory Hours: 3
Lab Hours: 2
Faculty: Kalligeros Emmanouil
Content outline

Application Specific Integrated Circuits (ASICs) and programmable devices (PLAs, PLDs, FPGAs), Hardware Description Languages (HDLs): Verilog and VHDL. Introduction to Verilog HDL, designing digital circuits with Verilog, Verilog syntax, modules and ports, structural modeling, behavioral modeling, dataflow modeling, tasks and functions. Finite State Machines (Mealy and Moore), Verilog for synthesis, design of sequential modules. Timing and delays in Verilog, Computer Aided Design (CAD) tools, logical simulation and timing verification. Random Access Memories (RAMs) and memory interfaces. Design prototyping.

Learning outcomes

Students who successfully fulfill the course requirements will know: the differences between programmable devices and ASICs, the main features of FPGAs structure, how to use Verilog HDL for designing combinational and sequential digital circuits, how to write testbenches in Verilog, how to write Verilog for synthesis, how to simulate their designs, the structure of RAMs and how to use them in digital systems, how to use prototyping boards for transferring their designs in hardware.

Not required.
Basic Textbooks
  1. Digital Design, A Systems Approach, W. J. Dally, R. C. Harting
  2. FPGA-Based System Design, Wayne Wolf
  3. Verilog HDL: A Guide to Digital Design and Synthesis, Samir Palnitkar, 2nd Ed.
Additional References
  • IEEE Transactions on VLSI Systems
  • IEEE Transactions on Computers
Learning Activities and Teaching Methods

Lab exercises (20%), Project (40%), Written examination (40%)

Assessment/Grading Methods

Lectures, Laboratory ασκήσεις, Εργασία

Activity Semester workload
Lectures 39 hours
Laboratory Exercises 26 hours
Εργασία 30 hours
Personal study 27 hours
Final exams 3 hours
Course total 125 hours (5 ECTS)


Language of Instruction
Greek, English (for Erasmus students)
Μode of delivery


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