Dr. Emmanouil Kalligeros

Address	Information and Communication Systems Engineering Department University of the Aegean 83200 Karlovassi, Samos, Greece
E-mail
Phone	+30 22730 82237
Office hours	Thursday, Friday 09:30-11:00 (Office: A3)

Teaching

      Logic Design

      Digital Systems Design

      Introduction to VLSI

      Embedded Systems (postgraduate)

Research Interests

• Hardware security
• Design of efficient digital systems for signal processing
• FPGA-based systems
• Network-on-Chip (NoC) architectures
• VLSI testing and Design for Testability (DFT)

  o  Built-In Self-Test (BIST)

  o  Test-data compression architectures

  o  Low-power testing

  o  Delay testing

• Computer-Aided Design (CAD) methodologies and tools for VLSI testing

Stuck-at fault Test Cubes for the ISCAS'89 benchmarks circuits: cubes.zip

Publications

Book

D. Drosos, D. Vouyioukas, E. Kalligeros, S. Kokolakis, C. Skianis, "Introduction to Computer Science and Communications: Technologies and Applications" (Greek Edition), Hellenic Academic Libraries Link (Ed.), Athens, 2016. 

Book chapter

G. Dimitrakopoulos, C. Kachris, and E. Kalligeros, "Switch Design for Soft Interconnection Networks", Chapter 6 in Embedded Systems Design with FPGAs, P. Athanas, D. Pnevmatikatos, and N. Sklavos (editors), pp. 125-147, 2013, Springer, ISBN: 978-1-4614-1361-5 (Print), 978-1-4614-1362-2 (Online). 

Journals

1. N. Limaye, E. Kalligeros, N. Karousos, I. G. Karybali, and O. Sinanoglu, "Thwarting All Logic Locking Attacks: Dishonest Oracle with Truly Random Logic Locking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear.

2. K. Pexaras, I. G. Karybali, and E. Kalligeros, "Optimization and Hardware Implementation of Image and Video Watermarking for Low Cost Applications", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, pp. 2088-2101, June 2019.

3. G. Dimitrakopoulos, E. Kalligeros, and K. Galanopoulos, "Merged Switch Allocation and Traversal in Network-On-Chip Switches", IEEE Transactions on Computers, vol. 62, pp. 2001-2012, October 2013.

4. X. Kavousianos, V. Tenentes, K. Chakrabarty, and E. Kalligeros, "Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, pp. 2330-2335, December 2011.

5. V. Tenentes, X. Kavousianos, and E. Kalligeros, "Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1640-1644, October 2010.

6. X. Kavousianos, E. Kalligeros, and D. Nikolos, "Test Data Compression Based on Variable-to-Variable Huffman Encoding with Codeword Reusability", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1333-1338, July 2008.

7. X. Kavousianos, E. Kalligeros, and D. Nikolos, "Multilevel Huffman Test-Data Compression for IP Cores with Multiple Scan Chains", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, pp. 926-931, July 2008.

8. X. Kavousianos, E. Kalligeros, and D. Nikolos, "Optimal Selective Huffman Coding for Test-Data Compression", IEEE Transactions on Computers, vol. 56, pp. 1146-1152, August 2007.

9. X. Kavousianos, E. Kalligeros, and D. Nikolos, "Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 1070-1083, June 2007.

10. E. Kalligeros, X. Kavousianos, and D. Nikolos, "Multiphase BIST: A New Reseeding Technique for High Test Data Compression", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 1429-1446, October 2004.

11. D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos, and G. Alexiou, "On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation", Journal of Systems Architecture, Elsevier, vol. 48, no. 4-5, pp. 125-135, December 2002.

12. E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, "On-the-fly Reseeding: A New Reseeding Technique for test-per-clock BIST", Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers (Springer), Special Issue on On-Line Testing, vol. 18, no. 3, pp. 315-332, June 2002.  

Conferences

1. E. Kalligeros, N. Karousos, and I. G. Karybali, "Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist", in Proc. of Design Automation and Test in Europe (DATE) Conference, March 2020, pp. 939-944.

2. S. Kotsilitis, E. C. Marcoulaki, and E. Kalligeros, "High frequency energy disaggregation sampling and analysis towards predictive maintenance applications", in Proc. of European Safety and Reliability Conference (ESREL), September 2019, pp. 1214-1221.

3. G. Vrettos, E. Logaras, and E. Kalligeros, "Towards standardization of MQTT-alert-based sensor networks: protocol structures formalization and low-end node security", in Proc. of IEEE International Symposium on Industrial Embedded Systems (SIES), June 2018.

4. S. Kotsilitis, E. C. Marcoulaki, E. Kalligeros, and Y. Mousmoulas, "Energy Efficiency and Predictive Maintenance Applications Using Smart Energy Measuring Devices", in Proc. of European Safety and Reliability Conference (ESREL), June 2018, pp. 987-994.

5. K. Pexaras, C. Tsiourakis, I. G. Karybali, and E. Kalligeros, "Optimization and Hardware Implementation of Image Watermarking for Low Cost Applications", in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2017, pp. 347-350.

6. N. Karousos, K. Pexaras, I. G. Karybali, and E. Kalligeros, "Weighted Logic Locking: A New Approach for IC Piracy Protection", in Proc. of IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2017, pp. 221-226.

7. S. Arakliotis, D. G. Nikolos, and E. Kalligeros, "LAWRIS: A Rule-Based Arduino Programming System for Young Students", International Conference on Modern Circuits and Systems Technologies (MOCAST), May 2016.

8. I. Seitanidis, A. Psarras, E. Kalligeros, C. Nicopoulos, and G. Dimitrakopoulos, "ElastiNoC: A Self-Testable Distributed VC-based Network-on-Chip Architecture", in Proc. of IEEE/ACM International Symposium on Networks-on-Chip (NOCS), September 2014, pp. 135-142.

9. G. Dimitrakopoulos, N. Georgiadis, C. Nicopoulos, and E. Kalligeros, "Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports", in Proc. of Design Automation and Test in Europe (DATE) Conference, March 2013, pp. 344-349.

10. G. Dimitrakopoulos and E. Kalligeros, "Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches", in Proc. of Design Automation and Test in Europe (DATE) Conference, March 2012, pp. 542-545.

11. G. Dimitrakopoulos and E. Kalligeros, "Low-Cost Fault-Tolerant Switch Allocator for Network-on-Chip Routers", in Proc. of Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC) Workshop, January 2012, pp. 25-28.

12. G. Dimitrakopoulos, C. Kachris, and E. Kalligeros, "Scalable Arbiters and Multiplexers for On-FPGA Interconnection Networks", in Proc. of International Conference on Field-Programmable Logic and Applications (FPL), September 2011, pp. 90-96.

13. X. Kavousianos, K. Chakrabarty, E. Kalligeros, and V. Tenentes, "Defect Coverage-Driven Window-Based Test Compression", in Proc. of IEEE Asian Test Symposium (ATS), December 2010, pp. 141-146.

14. M. Koutsoupia, E. Kalligeros, X. Kavousianos, and D. Nikolos, "LFSR-Based Test-Data Compression with Self-Stoppable Seeds", in Proc. of Design Automation and Test in Europe (DATE) Conference, April 2009, pp. 1482-1487.

15. V. Tenentes, X. Kavousianos, and E. Kalligeros, "Shrinking the Application Time of Test Set Embedding by Using Variable-State Skip LFSRs", in Informal Digest of Papers of IEEE European Test Symposium (ETS), May 2008.

16. V. Tenentes, X. Kavousianos, and E. Kalligeros, "State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores", in Proc. of Design Automation and Test in Europe (DATE) Conference, March 2008, pp. 474-479.

17. X. Kavousianos, E. Kalligeros, and D. Nikolos, "Test-Data Compression Based on Variable-to-Variable Reusable Huffman Coding", in Informal Digest of Papers of IEEE European Test Symposium (ETS), May 2007, pp. 253-258.

18. X. Kavousianos, E. Kalligeros, and D. Nikolos, "A Parallel Multilevel-Huffman Decompression Scheme for IP Cores with Multiple Scan Chains", in Informal Digest of Papers of IEEE European Test Symposium (ETS), May 2006, pp. 164-169.

19. E. Kalligeros, X. Kavousianos, and D. Nikolos, "Efficient Multiphase Test Set Embedding for Scan-based Testing", in Proc. of International Symposium on Quality Electronic Design (ISQED), March 2006, pp. 433-438.

20. X. Kavousianos, E. Kalligeros, and D. Nikolos, "Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding", in Proc. of Design Automation and Test in Europe (DATE) Conference, March 2006, pp. 1033-1038.

21. G. Gekas, D. Nikolos, E. Kalligeros, and X. Kavousianos, "Power Aware Test-Data Compression for Scan-based Testing", in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2005.

22. D. Kaseridis, E. Kalligeros, X. Kavousianos, and D. Nikolos, "An Efficient Test Set Embedding Scheme with Reduced Test Data Storage and Test Sequence Length Requirements for Scan-based Testing", in Informal Digest of Papers of IEEE European Test Symposium (ETS), May 2005, pp. 147-150.

23. E. Kalligeros, D. Kaseridis, X. Kavousianos, and D. Nikolos, "Reseeding-based Test Set Embedding with Reduced Test Sequences", in Proc. of International Symposium on Quality Electronic Design (ISQED), March 2005, pp. 226-231.

24. E. Kalligeros, X. Kavousianos, and D. Nikolos, "A Highly Regular Multiphase Reseeding Technique for Scan-based BIST", in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI), April 2003, pp. 295-298.

25. E. Kalligeros, X. Kavousianos, and D. Nikolos, "A ROMless LFSR Reseeding Scheme for Scan-based BIST", in Proc. of IEEE Asian Test Symposium (ATS), November 2002, pp. 206-211.

26. E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, "An Efficient Seeds Selection Method for LFSR-based Test-Per-Clock BIST", in Proc. of International Symposium on Quality Electronic Design (ISQED), March 2002, pp. 261-266.

27. E. Kalligeros, X. Kavousianos, D. Bakalis, and D. Nikolos, "A New Reseeding Technique for LFSR-based Test Pattern Generation", in Proc. of IEEE International On-Line Testing Workshop (IOLTW), July 2001, pp. 80-86.

28. D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos, and G. Alexiou, "Low Power BIST for Wallace Tree-based Fast Multipliers", in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), March 2000, pp. 433-438.

29. T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropoulos, Y. Tsiatouhas, and H.T. Vergos, "A Class of Easily Path Delay Fault Testable Circuits", in Proc. of Southwest Symposium on Mixed-Signal Design (SSMSD), February 2000, pp. 165-170.

30. E. Kalligeros, H. T. Vergos, D. Nikolos, Y. Tsiatouhas, and Th. Haniotakis, "Path Delay Fault Testable Modified Booth Multipliers", in Proc. of Design of Circuits and Integrated Systems Conference (DCIS), November 1999, pp. 301-306.

31. M. Bellos, E. Kalligeros, D. Nikolos, and H. T. Vergos, "On-Line Path Delay Fault Testing of Omega MINs", in Proc. of IEEE International On-Line Testing Workshop (IOLTW), July 1999, pp. 133-137.