Introduction: MOS transistors, CMOS logic, basic gates and memory elements, CMOS fabrication and layout. MOS transistor theory: ideal (long-channel) I-V characteristics, C-V characteristics, non-ideal I-V effects, DC transfer characteristics. Delay: RC delay model, linear delay model – Logical Effort (for a single stage and for paths), transistor sizing. Power dissipation: dynamic power, static power, energy-delay optimization, low-power circuit design. Interconnect: wire geometry, metal layers, wire modeling, delay, energy, noise, wire engineering. Process and environmental variations. Scaling. Combinational circuit design: circuit families, circuit pitfalls. Sequential circuit design: circuit design of latches and flip-flops, max-delay constraints, min-delay constraints, time borrowing, clock skew. Semiconductor memories.

A student who successfully fulfills the course requirements will have demonstrated:

• An ability to design static CMOS combinational and sequential logic at the transistor level, including mask layout.
• An ability to describe the general steps required for processing of CMOS integrated circuits.
• An ability to understand the accurate (non-ideal) MOS transistor behavior.
• An ability to estimate and optimize combinational circuit delay using RC delay models and logical effort.
• An ability to estimate and optimize interconnect delay and noise.
• An ability to define the different kinds of power dissipation in VLSI circuits, as well as approaches for reducing it.
• An ability to design for higher performance or lower area using alternative circuit families.
• An ability to describe and avoid common CMOS circuit pitfalls.
• An ability to compare the tradeoffs of sequencing elements including flip-flops, transparent latches, and pulsed latches.
• An ability to understand and calculate max-delay constraints, min-delay constraints and the time that can be borrowed in all sequencing cases mentioned above.
• An ability to describe the sources and effects of clock skew.
• An ability to design and evaluate integrated circuits using Computer Aided Design (CAD) tools.
• An ability to describe the structure and functionality of semiconductor memories.

Not required.

1. CMOS VLSI Design: A Circuits and Systems Perspective, Neil H. E. Weste and David M. Harris, 4th Ed.
2. Digital Integrated Circuits: A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, 2nd Ed.
3. CMOS Digital Integrated Circuits Analysis and Design, Sung-Mo Kang and Yusuf Leblebici, 3rd Ed.

• IEEE Transactions on VLSI Systems
• IEEE Transactions on Circuits and Systems I
• IEEE Transactions on Circuits and Systems II 

Lectures, resolving exercises, Laboratory Exercises.

Homework (30%), Project (30%), Written examination (40%)

Face-to-face.