Research staff
Pexaras Kostas
Personal Information
Copyright Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted or mass reproduced without the explicit permission of the copyright holder.
Conference Publications
K. Pexaras, C. Tsiourakis, I. G. Karybali, E. Kalligeros, "Optimization and Hardware Implementation of Image Watermarking for Low Cost Applications", IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 347-350, Dec, 2017, http://ieeexplore.ieee.org/stamp/stamp.j...
Abstract:
In many resource/ power constrained applications (e.g., in wireless-network nodes) there is a need for low cost hardware implementations of digital image watermarking techniques. However, to end up with such an implementation, a proper selection of a watermarking technique, based on performance and cost criteria, is not enough. For that reason, in this paper we introduce computation optimizations of the implemented algorithm to keep the integer portion of arithmetic operations at optimal size, and, hence, arithmetic units as small as possible. Additionally, the proposed architecture reutilizes those units in different computation steps, to further reduce implementation cost. The proposed design compares favorably with the already existing implementations, in terms of area, power and performance.
In many resource/ power constrained applications (e.g., in wireless-network nodes) there is a need for low cost hardware implementations of digital image watermarking techniques. However, to end up with such an implementation, a proper selection of a watermarking technique, based on performance and cost criteria, is not enough. For that reason, in this paper we introduce computation optimizations of the implemented algorithm to keep the integer portion of arithmetic operations at optimal size, and, hence, arithmetic units as small as possible. Additionally, the proposed architecture reutilizes those units in different computation steps, to further reduce implementation cost. The proposed design compares favorably with the already existing implementations, in terms of area, power and performance.
N. Karousos, K. Pexaras, I. G. Karybali, E. Kalligeros, "Weighted Logic Locking: A New Approach for IC Piracy Protection", IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 221-226, Jul, 2017, http://ieeexplore.ieee.org/stamp/stamp.j...
Abstract:
Logic locking has been successfully used for protecting digital circuits against IC piracy. Modern logic locking techniques offer significant security advantages, like high corruptibility of the locked circuit's outputs when applying random keys (= 50% Hamming Distance -HD- compared to the correct outputs), or resilience to the key-sensitization attack. However, there are no techniques to combine both advantages. To solve this problem, weighted logic locking is proposed in this paper. Instead of the conventional single key-input control, the proposed technique uses multiple key-inputs to control every key-gate. This new, weighted key-gate control is by construction immune to the key-sensitization attack, while by employing a new key-gate insertion metric, 50% HD is obtained even for circuits with many outputs. Additionally, weighted key-gate control increases dramatically the probability of any key-gate to corrupt the circuit’s values, which means that fewer key-gates are needed to achieve 50% HD. This way, execution time for locking the circuits is drastically reduced. Apart from these advantages, weighted logic locking is fairly "generic" and can be combined with other techniques to improve security (e.g., to thwart the SAT attack).
Logic locking has been successfully used for protecting digital circuits against IC piracy. Modern logic locking techniques offer significant security advantages, like high corruptibility of the locked circuit's outputs when applying random keys (= 50% Hamming Distance -HD- compared to the correct outputs), or resilience to the key-sensitization attack. However, there are no techniques to combine both advantages. To solve this problem, weighted logic locking is proposed in this paper. Instead of the conventional single key-input control, the proposed technique uses multiple key-inputs to control every key-gate. This new, weighted key-gate control is by construction immune to the key-sensitization attack, while by employing a new key-gate insertion metric, 50% HD is obtained even for circuits with many outputs. Additionally, weighted key-gate control increases dramatically the probability of any key-gate to corrupt the circuit’s values, which means that fewer key-gates are needed to achieve 50% HD. This way, execution time for locking the circuits is drastically reduced. Apart from these advantages, weighted logic locking is fairly "generic" and can be combined with other techniques to improve security (e.g., to thwart the SAT attack).